The present invention relates to an image output device and an image output control method.
In recent years, portable terminals which uses a liquid crystal display (LCD) have increased in number, and the importance of image display is rising, while the reduction in power consumption has presented a significant challenge. Normally, the liquid crystal display requires a high display refresh rate, and needs 60-Hz updating. However, the image generation is carried out at 30 Hz or lower, so the difference in the rates is absorbed by providing a frame buffer or the like.
Japanese Published Patent Application No. Hei.07-77958 discloses such an electronic plotting device having a frame buffer, which will be described with reference to FIG. 15.
FIG. 15 is a block diagram illustrating a structure of the electronic plotting device 1.
In FIG. 15, a data supply unit 10 comprises an intermediate data generation unit 11 for generating intermediate data from graphic element data, and a pictographic data generation unit 12 for generating pictographic data from the intermediate data which are generated by the intermediate data generation unit 11. The data supply unit 10 converts the graphic element data into the pictographic data which are dot data rows in order of the scanning by a visualization device, and supplies the pictographic data to an output selection unit 30 and a cluster control unit 60. Frame memories 20 and 21 each stores second internal pictographic data which are one frame of the pictographic data supplied by the output selection unit 30. In accordance with input of a R/W control signal from a control unit 50, the frame memories 20 and 21 set one of two modes, i.e., a writing mode of writing one frame of the pictographic data and a reading mode of reading the stored one frame of the pictographic data. The output selection unit 30 selects one of first internal pictographic data which are supplied by the data supply unit 10, third internal pictographic data which are supplied by the frame memories 20 or 21, and fourth internal pictographic data which are supplied by the cluster control unit 60. A data display unit 40 displays the output pictographic data which are supplied by the output selection unit 60. The control unit 50 controls the device in its entirety. The cluster control unit 60 controls plural frames of the pictographic data to confluent successively.
The operation of the so-constructed electronic plotting device 1 will be described.
When a unit timing signal for indicating a position on a time series of the output pictographic data which are supplied to the data display unit 40 is input to the control unit 50, the control unit 50 generates a local timing signal for the internal processing of the data supply unit 10 and the like. This signal is basically the unit timing signal or the one which is obtained by adjusting the phase of the unit timing signal, and a signal which controls the supply of graphic element data which are required to be controlled to be asynchronous to the local timing signal is further added.
In addition, the control unit 50 generates a plotting section specification signal for specifying one plotting section in one frame, and outputs the signal to the intermediate data generation unit 11. The intermediate data generation unit 11 refers to the input graphic element data, and outputs intersection coordinates of a pattern border and a plotting line within the specified plotting section to the pictographic data generation unit 12. The pictographic data generation unit 12 generates the first internal pictographic data.
The first internal pictographic data are input to the output selection unit 30 and the cluster control unit 60. The cluster control unit 60 polymerizes (composes) the supplied first internal pictographic data and the third internal pictographic data which are supplied by the frame memories 20 or 21, and output the fourth internal pictographic data to the output selection unit 30.
The output selection unit 30 selects one of the first internal pictographic data and the fourth internal pictographic data, and outputs selected data to the data display unit 40, or the frame memories 20 and 21, or the data display unit 40 as well as the frame memories 20 and 21. This selection process is carried out in accordance with the output control signal which is supplied by the control unit 50. The pictographic data which are supplied from the output selection unit 30 to the data display unit 40 are referred to as the output pictographic data, and the pictographic data which are supplied from the output selection unit 30 to the frame memories 20 and 21 are referred to as the second internal pictographic data. Two frame memories 20 and 21 are provided in the prior art, while the frame memories can be more than two.
When the output pictographic data are supplied to the data display unit 40, the data display unit 40 displays the data, and when the second pictographic data are supplied to the frame memories 20 and 21, the frame memories 20 and 21 output the third internal pictographic data to the output selection unit 30 and the cluster control unit 60.
In cases where the first internal pictographic data cannot be output to the data display unit 40 in real time, i.e., the frame rate is low, the first internal pictographic data from the data supply unit 10 are supplied to the frame memories 20 and 21, and the control unit 50 controls the output selection unit 30 so that the third internal pictographic data which are output from one of the frame memories 20 and 21 are supplied to the data display unit 40.
In the Institute of Electronics, Information and Communication Engineers (IECE) technological research report, Vol.100, No.42, xe2x80x9cIntegrated Circuitxe2x80x9d, an architecture which outputs data from a single DRAM is disclosed in xe2x80x9cA Development of a DMA Controller Unit in a MPEG4 Codec LSIxe2x80x9d, and the power consumption of LSI is described in Proc of CICC ""99, pp 69-72, May 1999, xe2x80x9cA MPEG4 Programmable Codec DSP with an Embedded Pre/Post-processing Enginexe2x80x9d. According to these documents, when an image of a CIF (352xc3x97288) size is subjected to 15 Hz-codec, the data transfer quantity related to a video interface (VIF) accounts for 41% of the entirety, and the operation ratio of a DMA bus and the operation ratio of the VIF are high. This is described with reference to FIG. 16.
FIG. 16 is a block diagram illustrating a structure of the MPEG4 codec LSI. This LSI comprises a processor 161, a video I/O interface 164, a host interface 160, and a DMA controller 163. Image data which are stored in a SDRAM 162 are suited for NTSC format images, and output to an NTSC encoder (DAC) 166 through the VIF 164 by 60 fields per sec. At this time, the power consumed in the entire chip except for the SDRAM 162 is about 640 mW.
Japanese Published Patent Application No. Hei.09-93578 discloses an image transmitter and an image receiver, which can easily convert the resolution of an image to be coded or decoded. In this image transmitter, a frame rate setting register is shown, and in the image receiver, the techniques related to a writing control and a reading control for a frame memory are shown, which are described with reference to FIGS. 17 and 18.
In the image transmitter shown in FIG. 17, a video signal is digitized by an A/D converter 19, and a switch is switched for each frame to input the signal to an image frame memory 22 or 23. A reading/writing control means 21 decides a pixel sampling method on the basis of a signal processing time of a QCIF image which is obtained by dividing an image of CCIR601 level, so as to have a frame rate within the one which is specified by a target frame rate setting means 26. To be more specific, in order to reduce the resolution of the input image, the CCIR601 level image is down-sampled by the reading/writing control means into plural QCIF images having different sampling positions. Then, the reading address is given to the image frame memories 22 and 23. A QCIF coding means 25 encodes an image of QCIF level by the DCT transformation and the quantization, and transmits coded image together with the QCIF number, to the receiver via a communication network 28.
In the image receiver shown in FIG. 18, a video signal which has been decoded by a decoding means 31 is written in an image frame memory 34 or 35. A reading/writing control means 33 selects one of the image frame memories 34 and 35 into which the signal is to be written. This is for the purpose of preventing the reading and the writing from simultaneously accessing the same memory, and switches 32 and 36 are alternately switched to be in opposite phases. The QCIF decoding means 31 detects that the decoding of the last QCIF in one frame (QCIF 3 in a case where one frame is divided into four pieces, and QCIF 15 in a case where one frame is divided into 16 pieces) has been completed, and notifies that to the reading/writing control means 33. That is, the switching of the switches 32 and 36 is instructed. When the reading/writing control means 33 is notified by the QCIF decoding means 31 that the decoding process for all QCIFs composing one frame has been finished, the reading/writing control means starts the reading of the video signal from the image frame memory 34 or 35, and reconstructs a CCIR601 image.
However, in the aforementioned prior art electronic plotting device, when the image composition is performed, an image is temporarily stored in the frame memory, composed with frame data which are transferred next, and thereafter output to an image display device. Therefore it takes at least one frame of delay to display a composed image.
In addition, in cases where the frame rate of a generated image is lower than the display rate of a data display unit, even when the display image is to be updated immediately, there is no updating means and further two frame memories alternately output data, whereby one frame of delay always occurs.
Further, when images which are to be updated immediately are two composed images having different frame rates, the composed images cannot be reflected immediately.
Furthermore, two frame memories are always required, resulting in an increased circuit scale, as well as it is necessary to read the temporarily stored data again from the frame memory to compose the same, thereby increasing the number of times of the data transfer, which leads an increase in the consumed power.
On the other hand, in the IECE technological research report, Vol.100, No.42, xe2x80x9cIntegrated Circuitxe2x80x9d, xe2x80x9cA Development of a DMA Controller Unit in a MPEG4 Codec LSIxe2x80x9d and Proc of CICC ""99, pp 69-72, May 1999, xe2x80x9cA MPEG4 Programmable Codec DSP with an Embedded Pre/Post-processing Enginexe2x80x9d describe that increases in the operation ratios of the DMD bus and the VIF lead to increases in the consumed powers of a logic and a memory. It is considered that this is because the access to the memory or the operation ratio of the logic is increased since it is required to output the NTSC images from a single memory by 60 fields per sec.
Japanese Published Patent Application No. Hei.09-93578 does not disclose a method in which a frame rate register exists in the transmitter while only a decode termination notification is included in the receiver, and frame data are displayed in a fixed cycle but the image display is sometimes carried out in asynchronization with the cycle, and a technique concerning the data transfer control for that purpose.
When a video processing unit for subjecting decoded images to various kinds of video processing such as scaling of images and noise elimination is to be provided, the video processing unit should be inserted between a selector and a D/A converter. Accordingly, the video processing unit works for each output frame, which leads to an increase in the power consumption.
Further, in cases where the video processing unit has no scheduling for data transfer, where data transfer requests are to be issued at one position, and where the display schedule is changed by the image display device, when the data transfer is requested at a timing which is decided by hardware, this cannot handle various devices flexibly.
Further, when two frame memories are provided and switched by the switch, four memories are required when plural images like moving images and graphics are to be processed, thereby increasing a circuit scale.
It is an object of the present invention to provide an image output device and an image output control method, which can update a display screen immediately by a minimum data transfer.
Other objects and advantages of the present invention will become apparent from the detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the spirit and scope of the invention will be apparent to those of skill in the art from the detailed description.
An image output device according to a 1st aspect of the present invention comprises a data memory for containing image data, a video processing unit for carrying out an image processing for the image data to generate display image data, a data transfer control unit for controlling data transfer between the data memory and the video processing unit, an output data storage unit for temporarily containing the display image data and outputting the display image data to an image display unit at regular intervals, and a system control unit for controlling the entire device, and this image output device comprises a data transfer request control circuit for issuing a data transfer request to execute the data transfer in units of prescribed data, only when the system control unit provides an update instruction for updating the display image data which are stored in the output data storage unit. Therefore, the data transfer is carried out only when the update flag is set in the frame update register, and thus the minimum data updating is carried out, whereby needless transfer can be omitted, and consequently the power consumption can be reduced. Further, when the update flag is set, the data transfer can be started automatically and immediately, whereby no complicated control exerted by the system control unit like in the prior art is required, as well as the image data can be immediately updated without delay.
According to a 2nd aspect of the present invention, in the image output device of the 1st aspect, the data transfer request control circuit comprises a data transfer request issuing unit for periodically issuing the data transfer request and a frame rate register for deciding a cycle of issuing the data transfer request, and this data transfer request issuing unit starts the issue of the data transfer request immediately at an issue start judgement timing of the data transfer request when an update flag is set in the frame rate register by the system control unit, regardless of the issue cycle which has been set in the frame rate register. Therefore, irregular data transfer requests can be immediately issued with maintaining the cycle of issuing the periodic data transfer request.
According to a 3rd aspect of the present invention, in the image output device of the 2nd aspect, the frame rate register comprises a counter for counting the issue start judgement timing of the data transfer request, a most significant bit is a bit which indicates the update flag, and lower bits except for the most significant bit decide the issue cycle, and when the update flag is effective, the counter is reset, the update flag is reset to an invalid value at an issue start judgement timing of the next data transfer request, and the counter counts again the issue cycle which has been decided by the lower bits except for the most significant bit. Therefore, the setting of the frame rate register and the counter can be automatically performed, and the transfer cycle and the transfer can be easily set, thereby requiring no resetting.
According to a 4th aspect of the present invention, in the image output device of the 3rd aspect, the frame rate register decides a transfer cycle which indicates a frame in which the data transfer request is to be issued, in a cycle of outputting images to the image display device, and the data transfer request issuing unit comprises a moving image transfer register for deciding whether transfer of moving image data is effective or invalid and a graphics transfer register for deciding whether transfer of graphics data is effective or invalid, and when the system control unit sets the update flag in the frame rate register, issues the data transfer request corresponding to the respective register only when the moving image register or the graphics register is effective. Therefore, the display image can be immediately updated, whereby the delay before the data display from the user""s operation can be reduced, thereby providing no unnatural video. Further, since no needless transfer of the moving image data is carried out, the power consumption in a case where the data transfer is not carried out can be reduced.
According to a 5th aspect of the present invention, in the image output device of the 4th aspect, the data transfer request issuing unit issues the data transfer request for each line at a timing of a horizontal synchronous signal among signals for use in image output to the image display device, in a frame where the data transfer is effective. Therefore, the timing when the issue of the data transfer request is started can be easily controlled without the need for a special timing generator, and the issued request for the data transfer can be controlled in a periodic transfer cycle, whereby the transfer request issue can be easily realized by hardware.
According to a 6th aspect of the present invention, in the image output device of the 5th aspect, when the update flag is set in the frame rate register, the data transfer request issuing unit judges that the update flag is effective at a timing of the next vertical synchronous signal among the signals for use in image output to the image display device, and issues the data transfer request for transferring said frame. Therefore, the issue of the data transfer request can be judged in frame units and the system can be easily and accurately controlled, whereby the disturbance in images and the like hardly occurs.
An image output device according to a 7th aspect of the present invention comprises a data memory for containing image data, a video processing unit for carrying out an image processing for the image data to generate display image data, a data transfer control unit for controlling data transfer between the data memory and the video processing unit, an output data storage unit for temporarily containing the display image data and outputting the display image data to an image display device at regular intervals, and a system control unit for controlling the entire device, and this image output device comprises a fixed cycle interruption generation unit for outputting an interrupt signal to the system control unit at regular intervals in accordance with signals for use in image output to the image display device, and the system control unit judges whether the data transfer is to be carried out in accordance with input of the interrupt signal, and in a case where the control unit judged that it is an interrupt timing when the transfer is to be carried out, issues a data transfer request for carrying out the data transfer to the data transfer control unit, and in a case where the control unit judged that it is not an interrupt timing when the transfer is to be carried out, does not issue the data transfer request. Therefore, the update pattern can be changed by the system control unit in any phase of the development, and especially the update can be performed even after the completion of the system, whereby the update can be freely programmed and the flexibility of the update pattern is increased.
According to an 8th aspect of the present invention, in the image output device of the 7th aspect, the system control unit issues a moving image transfer request for transferring moving image data which are stored in the data memory, and a graphics transfer request for transferring graphics data which are stored in the data memory, respectively. Therefore, the moving image data and the graphics data can be controlled to be transferred separately, thereby reducing the power consumption.
According to a 9th aspect of the present invention, in the image output device of the 1st aspect, the video processing unit comprises a scaling unit for scaling moving image data which are transferred from the data memory to generate display moving image data, and a graphics generation unit for subjecting graphics data which are transferred from the data memory to graphics generation to generate display graphics image data, and composes the display moving image data and the display graphics image data to be output. Therefore, the processings for the moving image data and the graphics data can be separately controlled.
According to a 10th aspect of the present invention, in the image output device of the 9th aspect, the output data storage unit comprises a line buffer for temporarily containing one line of output data from the video processing unit, and a frame memory for containing one frame of output data from the line buffer. Therefore, the control on the timing of writing the display image data into the frame memory can be facilitated, and the composition and display of images can be realized by one frame memory. Further, since the data are stored in the frame memory in frame units, no disturbance in images occurs and the image display can be realized by fewer circuits.
According to an 11th aspect of the present invention, in the image output device of the 9th aspect, the output data storage unit comprises a frame memory for containing one frame of output data from the video processing unit and successively outputting the stored data in units of one line, and a line buffer for containing output data from the frame memory. Therefore, when the display image data are output to the image display device, it is not required to exert a control by a RAS or CAS like the frame memory, whereby the control on the timing of outputting the display image data can be more easily executed than it is executed directly from the frame memory.
According to a 12th aspect of the present invention, in the image output device of the 1st or 7th aspect, the video processing unit comprises a scaling unit for scaling moving image data which are transferred from the data memory to generate display moving image data, and a graphics generation unit for subjecting graphics data which are transferred from the data memory to graphics generation to generate display graphics image data, and outputs the display moving image data and the display graphics image data to the output data storage unit, respectively. Therefore, the processings for the moving image data and the graphics data can be separately controlled, thereby reducing the power consumption.
According to a 13th aspect of the present invention, in the image output device of the 12th aspect, the output data storage unit comprises a moving image line buffer for temporarily containing one line of the display moving image data, a moving image frame memory for temporarily containing one frame of output data from the moving image line buffer, a graphics line buffer for temporarily containing one line of the display graphics image data, and a graphics frame memory for temporarily containing one frame of output data from the graphics line buffer, and composes the data stored in the moving image frame memory and the data stored in the graphics frame memory to be output to the image display device. Therefore, the display moving image data and the display graphics image data can be separately stored, and no disturbance such as disappearance of video occurs. Further, these data can be separately updated, and the transfer of both image data is not always required, whereby the needless data transfer can be dispensed with and the power consumption can be reduced.
According to a 14th aspect of the present invention, in the image output device of the 12th aspect, the output data storage unit comprises a moving image frame memory for temporarily containing one frame of the display moving image data and successively outputting the stored display moving image data in units of one line, a moving image line buffer for temporarily containing output data from the moving image frame memory, a graphics frame memory for temporarily containing one frame of the display graphics image data and successively outputting the stored display graphics image data in units of one line, and a graphics line buffer for temporarily containing output data from the graphics frame memory, and composes the data stored in the moving image line buffer and the data stored in the graphics line buffer or separately output the data to the image display device. Therefore, even when the moving image data and the graphics data have different video formats, the data can be output individually in synchronization with the display line. In addition, even in cases where the numbers of display lines do not always coincident each other, such as a case where the same graphics image data are repeatedly output, it is not required to always read the data from the frame memory for each display line, thereby reducing the power consumption significantly.
According to a 15th aspect of the present invention, in the image output device of the 12th aspect, the output data storage unit comprises a moving image frame memory for temporarily containing one frame of the display moving image data and successively outputting the stored display moving image data in units of one line, a graphics frame memory for temporarily containing one frame of the display graphics image data and successively outputting the stored display graphics image data in units of one line, and a line buffer for composing output data from the moving image frame memory and output data from the graphics frame memory and temporarily containing the composed data. Therefore, the display moving image data and the display graphics data can be separately updated, and consequently the needless data transfer can be dispensed with and the power consumption can be reduced.
According to a 16th aspect of the present invention, in the image output device of the 12th aspect, the output data storage unit comprises a moving image line buffer for temporarily containing one line of the display moving image data, a moving image frame memory for temporarily containing one frame of output data from the moving image line buffer and outputting the stored display moving image data in units of one line, a graphics line buffer for temporarily containing one line of the display graphics image data, a graphics frame memory for temporarily containing one frame of output data from the graphics line buffer and outputting the stored display graphics image data in units of one line, and a line buffer for composing output data from the moving image frame memory and output data from the graphics frame memory, temporarily containing the composed data as display image data, and outputting the display image data to the image display device. Therefore, the display moving image data and the display graphics data can be separately updated, and further the respective operations of the circuits can be reduced, whereby the needless data transfer is dispensed with and the power consumption can be reduced.
According to a 17th aspect of the present invention, in the image output device of the 12th aspect, the output data storage unit comprises a first moving image line buffer for temporarily containing one line of the display moving image data, a moving image frame memory for temporarily containing one frame of output data from the first moving image line buffer and successively outputting the stored display moving image data in units of one line, a second moving image line buffer for temporarily containing output data from the moving image frame memory, a first graphics line buffer for temporarily containing one line of the display graphics image data, a graphics frame memory for temporarily containing one frame of output data from the first graphics line buffer and successively outputting the stored display graphics image data in units of one line, and a second graphics line buffer for temporarily containing output data from the graphics frame memory, and composes the data stored in the second moving image line buffer and the data stored in the second graphics line buffer to be output to the image display device. Therefore, the operation of the large capacity frame memory which stores one frame of image data for image display in a case where the image update is not carried out can be minimized, to reduce the power consumption significantly, as well as the data update of the display moving image data and the display graphics image data can be separately carried out, and further even when the moving image data and the graphics data have different video formats, the data can be output to the image display device individually in synchronization with the display line.
According to a 18th aspect of the present invention, the image output device of the 1st or 7th aspect comprises an operation clock stop control unit for controlling operation clocks in the device to be stopped when the data transfer or the data processing is not carried out. Therefore, the operation clocks of the moving image data processing system and the graphics image data processing system can be separately controlled in accordance with the data transfer of the moving image data or the graphics image data, whereby the power consumption can be reduced significantly.
According to a 19th aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 10th aspect to an image display device comprising: storing the display image data in the line buffer in a period except for a blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; transferring the display image data from the line buffer to the frame memory in the blanking period of the horizontal synchronous signal; and outputting the display image data from the frame memory to the image display device in a period except for the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the frame memory and output the stored data immediately by utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetitive display in the next frame can be also performed, and the access contention to the frame memory can be avoided, whereby the system control can be easily executed. Further, one frame of the data can be stored in the frame memory to reduce the operation time, thereby reducing the power consumption.
According to a 20th aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 11th aspect to an image display device comprising: storing the display image data in the frame memory in a period except for the blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; transferring the display image data from the frame memory to the line buffer in the blanking period of the horizontal synchronous signal; and outputting the display image data from the line buffer to the image display device in a period except for the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the frame memory and immediately output the stored data with utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetitive display in the next frame can be also performed, and the access contention to the frame memory can be avoided, whereby the system can be easily controlled. Further, one frame of the data are stored in the frame memory to reduce the operation time, whereby the power consumption can be reduced.
According to a 21st aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 13th aspect to an image display device comprising: storing the display moving image data and the display graphics image data in the moving image line buffer and the graphics line buffer, respectively, in a period except for the blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; transferring the display moving image data and the display graphics image data from the moving image line buffer and the graphics line buffer to the moving image frame memory and the graphics frame memory, respectively, in the blanking period of the horizontal synchronous signal; and composing the display moving image data and the display graphics image data to be output to the image display device in a period except for the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the frame memory and immediately output the stored data by utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetitive display in the next frame can be also performed, and the access contention to the frame memory can be avoided, whereby the system can be easily controlled. Further, one frame of the data are stored in the frame memory to reduce the operation time, whereby the power consumption can be reduced.
According to a 22nd aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 14th aspect to an image display device comprising: storing the display moving image data and the display graphics image data in the moving image frame memory and the graphics frame memory, respectively, in a period except for a blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; transferring the display moving image data and the display graphics image data from the moving image frame memory and the graphics frame memory to the moving image line buffer and the graphics line buffer, respectively, in the blanking period of the horizontal synchronous signal; and composing the display moving image data and the display graphics image data or separately outputting the same to the image display device in a period except for the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to output the data which are stored in the frame memory to the line buffer with utilizing the effective period of the horizontal synchronous signal, the data of a line which is generated in the video processing unit can be output in the next line, whereby no data access contention to the frame memory occurs, and the frame delay can be reduced. Further, one frame of the data can be stored in the frame memory to reduce the operation time, thereby reducing the power consumption.
According to a 23rd aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 15th aspect to an image display device comprising: storing the display moving image data and the display graphics image data in the moving image frame memory and the graphics frame memory, respectively, in a period except for a blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; composing output data from the moving image frame memory and output data from the graphics frame memory to be transferred to the line buffer in the blanking period of the horizontal synchronous signal; and outputting the data stored in the line buffer to the image display device in a period except for the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the frame memory and immediately output the stored data with utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetition display in the next frame can be also performed, and the access contention to the frame memory can be avoided, whereby the system can be easily controlled. Further, one frame of the data can be stored in the frame memory to reduce the operation time, whereby the power consumption can be reduced.
According to a 24th aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 16th aspect to an image display device comprising: transferring data stored in the moving image line buffer and data stored in the graphics line buffer to the moving image frame memory and the graphics frame memory, respectively, in a half of a blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; and composing output data from the moving image frame memory and output data from the graphics frame memory to be transferred to the line buffer in the other half of the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the frame memory and immediately output the stored data with utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetition display in the next frame can be also performed, and the access contention to the frame memory can be avoided, whereby the system can be easily controlled. Further, one frame of the data can be stored to reduce the operation time, thereby reducing the power consumption.
According to a 25th aspect of the present invention, there is provided an image output control method for controlling output of image data from the image output device of the 17th aspect to an image display device comprising: transferring the data stored in the first moving image line buffer and the data stored in the first graphics line buffer to the moving image frame memory and the graphics frame memory, respectively, in a half of a blanking period of a horizontal synchronous signal among signals for use in image output to the image display device; and transferring the data stored in the moving image frame memory and the data stored in the graphics frame memory to the second moving image line buffer and the second graphics line buffer, respectively, in the other half of the blanking period of the horizontal synchronous signal. Therefore, the control is exerted to store the data in the moving frame memory and the graphics frame memory and immediately output the stored data with utilizing the effective period of the horizontal synchronous signal, thereby reducing the frame delay, as well as the repetition display in the next frame can be also performed, and the access contention to the moving image frame memory and the graphics frame memory can be avoided, whereby the system can be easily controlled. Further, one frame of the data can be stored in the frame memories to reduce the operation times, whereby the power consumption can be reduced.